1. Field of the Invention
The present invention relates to a field effect transistor (FET) operated with low noise at high speed.
2. Related Background Art
Japanese Patent Laid-Open No. 63-90861, Japanese Patent Laid-Open No. 63-272080, and Japanese Patent Laid-Open No. 64-2371 disclose techniques related to an FET using n-type GaInAs as a channel.
In these techniques, since Si is uniformly doped in GaInAs, electrons serving as carriers are scattered by Si atoms, and a sufficient overshoot-effect of drift velocity cannot be obtained and therefore sufficient characteristics to operate with low noise at high speed cannot be obtained. In Japanese Patent Laid-Open No. 63-90861, a technique for planer-doping Si in a GaInAs layer is disclosed. However, an FET having a deep gate threshold value voltage Vth cannot easily be formed by that planer-doping. For this reason, the following problems rises. That is, 1 an FET having a high output cannot be formed, and 2 the degree of freedom of circuit design is low.